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LOS GATOS, Calif.--(BUSINESS WIRE)--June 4, 2001-- TransEDA PLC, the leader in functional verification for electronic system-on-chip (SoC), application specific integrated circuit (ASIC) and field programmable gate array (FPGA) designs, will debut its latest lineup of ready-to-use verification solutions at the Design Automation Conference, June 18-21 in Las Vegas.

At the conference, TransEDA will demonstrate its new Foundation Models library of system-level verification IP (intellectual property). The library offers robust, field-proven processor bus functional models, standard bus agents and monitors, and functional coverage models for use in existing HDL verification environments or with TransEDA's other products. The library currently supports the PCI local bus, Intel® Pentium(TM) and Itanium(TM) processors and the Vr5400(TM) MIPS® processor from NEC®. Foundation Models are available now and have a starting price of $10,000 for a one-year subscription license.

TransEDA sees its Foundation Models as the answer to the latest crisis in the evolution of the Electronic Design Automation (EDA) industry.

``Nearly a decade ago, there was a design productivity crisis. Silicon capacity was growing much faster than the ability of designers to design,'' said Tom Borgstrom, TransEDA vice president of marketing. ``People really needed another way of designing. The revolution that happened was design re-use -- using third-party IP or internally re-used blocks.''

``Today there is a verification productivity crisis. Functional verification consumes over 70% of the overall IC development cycle and is the key issue facing IC developers trying to reduce IC development time. As Design IP solved the design productivity crisis, we believe ready-to-use Verification IP will solve the verification productivity crisis,'' Borgstrom said.

TransEDA will also introduce a new product, VN-Control, an application-specific test automation tool for HDL designs. VN-Control features automatic test generation and results checking from a high-level test template; no new languages are needed. It can be used with Foundation Models and leading HDL simulators to provide a complete ready-to-use test environment for target applications. VN-Control is available now and has a starting price of $5,000 for a one-year subscription license.

TransEDA also will preview the next release of its Verification Navigator environment at DAC, including a new functional coverage analysis capability that uses pre-defined functional coverage models for standard interfaces and user-written models for custom functional coverage.

``We're providing what our customers demanded -- a ready-to-use functional coverage tool that doesn't require learning a new language,'' Borgstrom said.

Typically, engineers use code or structural coverage to track what has not yet been verified. But what they need is a product to help them track the functions that have been validated. TransEDA's new functional coverage tool measures whether a verification test covers the desired behavior or requirement. It tells the engineers whether they have implemented what they intended and what other functionality needs to be tested to ensure a fully verified design.

Those who receive a product demonstration at TransEDA's booth at DAC will receive a free copy of the second edition of the Verification Methodology Manual: Techniques for Verifying HDL Designs. The second edition expands on the original with updates on coverage analysis and new chapters on HDL checking and pre-silicon validation.

``It's a practical, hands-on resource for verification engineers to help them understand new approaches to verification,'' Borgstrom said.

TransEDA invites anyone interested in a demonstration of its latest products to stop by Booth 1701 at DAC or to request a private suite demo at www.transeda.com/dac.

About TransEDA

TransEDA PLC (symbol TRA on the London Stock Exchange) develops and markets ready-to-use verification solutions for electronic field programmable gate array (FPGA), application-specific integrated circuit (ASIC) and system on a chip (SoC) designs. The company's verification IP library includes models for advanced microprocessors and bus interfaces. The company's design verification software performs application specific test automation, configurable HDL checking, functional, FSM and code coverage analysis and test suite analysis. TransEDA's tier-1 list of customers includes 18 of the top 20 semiconductor vendors.

For more information, contact TransEDA at 985 University Avenue, Los Gatos, Calif. 95032, telephone 408/335-1300, fax 408/335-1319, e-mail info@transeda.com, or visit http://www.transeda.com.

     TransEDA
     Tom Borgstrom, 408/335-1303
     tom.borgstrom@transeda.com
          or
     Cayenne Communication
     Michelle Clancy, 252/940-0981
     michelle.clancy@cayennecom.com
          or
     PentaCom
     Sharon Graves, +44 1242 525205
     sharon.graves@btinternet.com